AN H.264/AVC decoder with 4x4-block level pipeline

Ting An Lin*, Sheng Zen Wang, Tsu Ming Liu, Chen-Yi Lee

*此作品的通信作者

    研究成果: Conference article同行評審

    27 引文 斯高帕斯(Scopus)

    摘要

    In this paper, we propose a 4×4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1][2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.

    原文English
    文章編號1464961
    頁(從 - 到)1810-1813
    頁數4
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    DOIs
    出版狀態Published - 2005
    事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    持續時間: 23 5月 200526 5月 2005

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