An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis

Shan Hui Chou*, Ting Yun Hsiao, Jing Yang Jou, Juinn Dar Huang

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

Systolic array is one of the popular convolutional neural network accelerator architectures due to its high computation efficiency. Nevertheless, the huge design space and complicated interactions among different design parameters make it hard to find the best configuration for various applications. To overcome this issue, this paper presents an evaluation and design space exploration engine, NNeed, for systolic-array CNN accelerators through extensive dataflow analysis. It uses a highly configurable hardware template to describe accelerator operations in detail. The rapid evaluation provides PPA results, pipeline stage analysis, external memory access statistics, and so on. NNeed explores the 9-dimensional design space and supports multiple objective functions for design optimization. Experimental results show that NNeed can generate an accelerator configuration with up to 23% and 50% improvement in performance and energy as compared with a typical handcrafted design.

原文English
主出版物標題2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
發行者IEEE Computer Society
ISBN(電子)9798350325997
DOIs
出版狀態Published - 2023
事件31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023 - Dubai, United Arab Emirates
持續時間: 16 10月 202318 10月 2023

出版系列

名字IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN(列印)2324-8432
ISSN(電子)2324-8440

Conference

Conference31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023
國家/地區United Arab Emirates
城市Dubai
期間16/10/2318/10/23

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