An energy-efficient approximate systolic array based on timing error prediction and prevention

Ning Chi Huang, Wei Kai Tseng, Huan Jan Chou, Kai Chiang Wu

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

Deep neural networks (DNNs) have achieved out-standing accuracy on machine learning applications. However, the numbers of parameters and computational costs of DNNs have grown dramatically. To accelerate the numerous matrix multiplication operations in DNNs, a systolic array of multiplyand-accumulate units (MACs) is a widely-used architecture. In this paper, both timing error prediction and approximate computing are leveraged to relax the timing constraints of MACs. Afterwards, voltage underscaling is applied to further enhance the energy efficiency of the systolic array. In the experiments, our proposed approximate systolic array can obtain 36% energy reduction with only 1% accuracy loss for CFAR-10 image classification.

原文English
主出版物標題Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021
發行者IEEE Computer Society
ISBN(電子)9781665419499
DOIs
出版狀態Published - 25 4月 2021
事件39th IEEE VLSI Test Symposium, VTS 2021 - San Diego, United States
持續時間: 26 4月 202128 4月 2021

出版系列

名字Proceedings of the IEEE VLSI Test Symposium
2021-April

Conference

Conference39th IEEE VLSI Test Symposium, VTS 2021
國家/地區United States
城市San Diego
期間26/04/2128/04/21

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