An Energy-Efficient Accelerator with Relative-Indexing Memory for Sparse Compressed Convolutional Neural Network

I. Chen Wu, Po Tsang Huang, Chin Yang Lo, Wei Hwang

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

Deep convolutional neural networks (CNNs) are widely used in image recognition and feature classification. However, deep CNNs are hard to be fully deployed for edge devices due to both computation-intensive and memory-intensive workloads. The energy efficiency of CNNs is dominated by off-chip memory accesses and convolution computation. In this paper, an energy-efficient accelerator is proposed for sparse compressed CNNs by reducing DRAM accesses and eliminating zero-operand computation. Weight compression is utilized for sparse compressed CNNs to reduce the required memory capacity/bandwidth and a large portion of connections. Thus, ReLU function produces zero-valued activations. Additionally, the workloads are distributed based on channels to increase the degree of task parallelism, and all-row-to-all-row non-zero element multiplication is adopted for skipping redundant computation. The simulation results over the dense accelerator show that the proposed accelerator achieves 1.79x speedup and reduces 23.51%, 69.53%, 88.67% on-chip memory size, energy, and DRAM accesses of VGG-16.

原文English
主出版物標題Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
發行者Institute of Electrical and Electronics Engineers Inc.
頁面42-45
頁數4
ISBN(電子)9781538678848
DOIs
出版狀態Published - 3月 2019
事件1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 - Hsinchu, Taiwan
持續時間: 18 3月 201920 3月 2019

出版系列

名字Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019

Conference

Conference1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
國家/地區Taiwan
城市Hsinchu
期間18/03/1920/03/19

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