An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters

Bing-Fei Wu*, Yi Qiang Hu

*此作品的通信作者

研究成果: Letter同行評審

16 引文 斯高帕斯(Scopus)

摘要

This work presents a VLSI design rule, namely, an embedded instruction code (EIC), for the discrete wavelet transform (DWT). Our approach derives from the essential computations of DWT, and we establish a set of multiplication instructions, MUL, and the addition instruction, ADD. In addition, we propose a parallel arithmetic logic unit (PALU) with two multipliers and four adders, called 2M4A. With these requirements, the DWT computation paths can be calculated more efficiently with limited PALUs. Furthermore, since the EIC is operated under the PALU, the number of needed inner registers depends on the wavelet filters' length. Besides, the boundary problem of DWT has also been resolved by the symmetric extension. Moreover, the two-dimensional inverse DWT (2-D IDWT) can be completed using the same PALU for 2-D DWT; the only changes needed to be made are the instruction codes and coefficients. Our chip supports up to six levels of decomposition and versatile image specifications, e.g., VGA, MPEG-1, MPEG-2 and 1024 × 1024 image sizes.

原文English
文章編號1233005
頁(從 - 到)936-943
頁數8
期刊IEEE Transactions on Circuits and Systems for Video Technology
13
發行號9
DOIs
出版狀態Published - 1 9月 2003

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