TY - JOUR

T1 - An efficient parallel adder based design for one dimensional discrete Fourier transform

AU - Guo, Jiun-In

PY - 2000/5

Y1 - 2000/5

N2 - This paper presents a new efficient parallel adder (PA) based design for the one-dimensional (1-D) any-length discrete Fourier transform (DFT). Using the Chirp-Z transform, the author develops an algorithm which can formulate the 1-D any-length DFT as cyclic convolutions. This algorithm exhibits higher flexibility in the transform length as compared with the existing approaches to prime length DFT or power-of-two designs. In addition, the proposed design exploits the good feature of cyclic convolution to maximize intermediate data utilization in computing the output samples in a given DFT. Moreover, the proposed design uses parallel adders instead of multipliers as well as the Booth encoding scheme in the hardware realization for the sake of reducing the hardware cost. For example, in the case of 16-bit data wordlength, the proposed design can reduce the gate area by 30% to 90% as compared with the existing different DFT designs. In summary, the presented design has the benefits of low hardware cost, low input/output (I/O) cost, high computing speed and flexibility in the transform length.

AB - This paper presents a new efficient parallel adder (PA) based design for the one-dimensional (1-D) any-length discrete Fourier transform (DFT). Using the Chirp-Z transform, the author develops an algorithm which can formulate the 1-D any-length DFT as cyclic convolutions. This algorithm exhibits higher flexibility in the transform length as compared with the existing approaches to prime length DFT or power-of-two designs. In addition, the proposed design exploits the good feature of cyclic convolution to maximize intermediate data utilization in computing the output samples in a given DFT. Moreover, the proposed design uses parallel adders instead of multipliers as well as the Booth encoding scheme in the hardware realization for the sake of reducing the hardware cost. For example, in the case of 16-bit data wordlength, the proposed design can reduce the gate area by 30% to 90% as compared with the existing different DFT designs. In summary, the presented design has the benefits of low hardware cost, low input/output (I/O) cost, high computing speed and flexibility in the transform length.

KW - Cyclic convolution

KW - Discrete Fourier transform

KW - Parallel adder-based realization

UR - http://www.scopus.com/inward/record.url?scp=0033888466&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0033888466

SN - 0255-6588

VL - 24

SP - 195

EP - 204

JO - Proceedings of the National Science Council, Republic of China, Part A: Physical Science and Engineering

JF - Proceedings of the National Science Council, Republic of China, Part A: Physical Science and Engineering

IS - 3

ER -