An efficient memory-based FFT architecture

Chao Kai Chang*, Chung Ping Hung, Sau-Gee Chen

*此作品的通信作者

    研究成果: Conference article同行評審

    21 引文 斯高帕斯(Scopus)

    摘要

    This paper proposes an efficient memory-based radix-2 FFT architecture, which greatly improves the memory-based FFT [5], [6] by reducing 50% memory size requirement, while maintaining a simple address generator. Specifically the memory size is reduced to 1.25N words. In addition, the multiplier utilization rate is 100%.

    原文English
    頁(從 - 到)II129-II132
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    2
    DOIs
    出版狀態Published - 2003
    事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
    持續時間: 25 5月 200328 5月 2003

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