TY - JOUR
T1 - An efficient dual-interpolator architecture for subpixel motion estimation
AU - Wang, Yueh Yi
AU - Tsai, Chun-Jen
PY - 2005
Y1 - 2005
N2 - New generation of video codecs typically adopts a sophisticated interpolation filter for sub-pixel motion estimation (ME). For embedded applications, it is crucial to reduce both the memory requirement and the computational complexity for sub-pixel ME. The key observation in this paper is that the interpolation filter for motion estimation and the filter for coding do not have to be the same. By adopting a simpler on-the-fly interpolation filter during ME process and a standard-compliant filter for coding purpose, both memory and complexity can be reduced with very little coding performance degradation. Since Hadamard transformed-SAD is often used in high quality codecs as a better matching measure, we further show that the ME interpolation filer can be combined with Hadamard transform for efficient VLSI implementation. Initial results show very promising performance of the proposed system.
AB - New generation of video codecs typically adopts a sophisticated interpolation filter for sub-pixel motion estimation (ME). For embedded applications, it is crucial to reduce both the memory requirement and the computational complexity for sub-pixel ME. The key observation in this paper is that the interpolation filter for motion estimation and the filter for coding do not have to be the same. By adopting a simpler on-the-fly interpolation filter during ME process and a standard-compliant filter for coding purpose, both memory and complexity can be reduced with very little coding performance degradation. Since Hadamard transformed-SAD is often used in high quality codecs as a better matching measure, we further show that the ME interpolation filer can be combined with Hadamard transform for efficient VLSI implementation. Initial results show very promising performance of the proposed system.
UR - http://www.scopus.com/inward/record.url?scp=41049117175&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465235
DO - 10.1109/ISCAS.2005.1465235
M3 - Conference article
AN - SCOPUS:41049117175
SN - 0271-4310
SP - 2907
EP - 2910
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1465235
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -