An efficient design for one-dimensional discrete hartley transform using parallel additions

Jiun-In Guo*

*此作品的通信作者

研究成果: Article同行評審

19 引文 斯高帕斯(Scopus)

摘要

This paper presents a new efficient design for the onedimensional (1-D) any-length discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, an algorithm that can formulate the 1-D any-length DHT as cyclic convolutions is developed. This algorithm owns higher flexibility in the transform length as compared with the existing approaches for prime length DHT or power-of-two DHT designs. Moreover, the proposed design exploits the good feature of cyclic convolution and uses parallel adders instead of multipliers in the hardware realization. The presented design not only possesses low hardware cost but also owns low input/output (I/O) cost, high computing speeds, and flexibility in transform length.

原文English
頁(從 - 到)2806-2813
頁數8
期刊IEEE Transactions on Signal Processing
48
發行號10
DOIs
出版狀態Published - 1 10月 2000

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