TY - JOUR
T1 - An Efficient Decoder Architecture for Nonbinary LDPC Codes with Extended Min-Sum Algorithm
AU - Lin, Chia Lung
AU - Tu, Shu Wen
AU - Chen, Chih-Lung
AU - Chang, Hsie-Chia
AU - Lee, Chen-Yi
PY - 2016/9/1
Y1 - 2016/9/1
N2 - Nonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, provide stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms have been proposed in the literature, and the extended min-sum (EMS) algorithm is the one with minimal performance loss. In this brief, we present an efficient decoder architecture for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but also overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed as well. With these schemes, the postlayout results of a decoder for a (112, 56) NB-LDPC over GF(64) are presented. The core area occupies 2.24 mm2 and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware efficiency and energy efficiency.
AB - Nonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, provide stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms have been proposed in the literature, and the extended min-sum (EMS) algorithm is the one with minimal performance loss. In this brief, we present an efficient decoder architecture for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but also overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed as well. With these schemes, the postlayout results of a decoder for a (112, 56) NB-LDPC over GF(64) are presented. The core area occupies 2.24 mm2 and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware efficiency and energy efficiency.
KW - Decoding scheduling
KW - extended min-sum (EMS) algorithm
KW - nonbinary low-density-parity-check (NB-LDPC) codes
KW - Very large scale integration (VLSI)
UR - http://www.scopus.com/inward/record.url?scp=84985896375&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2016.2534820
DO - 10.1109/TCSII.2016.2534820
M3 - Article
AN - SCOPUS:84985896375
SN - 1549-8328
VL - 63
SP - 863
EP - 867
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 9
M1 - 7419880
ER -