An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs

Keyphrases

• Behavioral Model 100%
• Extraction Approach 100%
• Main Idea 25%
• HSPICE 25%
• Input Pattern 25%
• Two-input 25%
• Parasitic Effects 25%
• PLL Circuit 25%
• Circuit Parameters 25%
• Verilog-AMS 25%
• Critical Circuit 25%

Engineering

• Phase Locked Loop 100%
• Behavioral Model 100%
• Experimental Result 25%
• Circuit Parameter 25%
• Main Idea 25%
• Input Pattern 25%

Computer Science

• Phase Locked Loop 100%
• Experimental Result 25%
• Verilog 25%