An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL circuits more quickly by using Verilog-AMS language. Not only top-down applications but also bottom-up applications can be supported by using our PLL models. The main idea is to use a special "characterization mode" to get critical circuit parameters. In the characterization mode, only two input patterns are enough to get circuit properties with parasitic effects. In the experimental results, we will build an accurate PLL behavioral models for demonstration compared to the HSPICE results and typical behavioral models.