An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs

Chin Cheng Kuo*, Yu Chien Wang, Chien-Nan Liu

*此作品的通信作者

研究成果: Paper同行評審

6 引文 斯高帕斯(Scopus)

摘要

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL circuits more quickly by using Verilog-AMS language. Not only top-down applications but also bottom-up applications can be supported by using our PLL models. The main idea is to use a special "characterization mode" to get critical circuit parameters. In the characterization mode, only two input patterns are enough to get circuit properties with parasitic effects. In the experimental results, we will build an accurate PLL behavioral models for demonstration compared to the HSPICE results and typical behavioral models.

原文English
頁面286-290
頁數5
DOIs
出版狀態Published - 29 12月 2005
事件2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
持續時間: 17 4月 200519 4月 2005

Conference

Conference2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
國家/地區United States
城市Chicago, IL
期間17/04/0519/04/05

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