An efficient application processor architecture for multicore software video decoding

Keyphrases

• Proposed Architecture 100%
• Processor Architecture 100%
• Video Decoding 100%
• Software pipeline 100%
• Multicore Software 100%
• Application-specific Processors 100%
• Pipeline Parallelism 66%
• Symmetric multiprocessor 66%
• Field Programmable Gate Arrays 33%
• Parallelization 33%
• On-a-chip 33%
• Operating System 33%
• Programmer 33%
• Video Decoder 33%
• Baseline Profile 33%
• Pipeline Stages 33%
• Fine Granularity 33%
• Programming Model 33%
• System Call 33%
• Advanced Video Coding 33%
• Development Board 33%
• System Buses 33%
• Reduced Instruction Set Computing 33%
• Parallel Software 33%
• Multicore Application 33%

Computer Science

• Multicore 100%
• Application Processor 100%
• Processor Architecture 100%
• Parallelism 66%
• Datapath 66%
• Symmetric Multi-Processor 66%
• Pipeline Parallelism 66%
• Programming Model 33%
• Experimental Result 33%
• Baseline Profile 33%
• System on a Chip 33%
• Pipeline Stage 33%
• Fine Granularity 33%
• System Calls 33%
• Development Board 33%
• Target Platform 33%
• Reduced Instruction Set Computing 33%
• Chip Architecture 33%
• Field Programmable Gate Arrays 33%
• Operating System 33%