An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm

Wei Yeh Shih; Kuan Ju Huang; Chiu Kuo Chen; Wai-Chi  Fang; Gert Cauwenberghs; Tzyy Ping Jung

doi:10.1109/BioCAS.2012.6418464

An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm

Wei Yeh Shih^*, Kuan Ju Huang, Chiu Kuo Chen, Wai-Chi Fang, Gert Cauwenberghs, Tzyy Ping Jung

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

8 引文斯高帕斯（Scopus）

摘要

This paper presents an effective chip implementation of a real-time eight-channel electroencephalogram signal processor based on on-line recursive independent component analysis (ORICA) algorithm. The system architecture is composed of a memory unit, a whitening unit, an ORICA training unit, and an ORICA computation unit. The proposed architecture is implemented using TSMC 90 nm CMOS technology. It occupies a core area of 800×800 μm² and consumes 4.18 mW at a core supply voltage of 1.0 V and 50 MHz clock operating frequency. Simulated super and sub-Gaussian signals are used to verify the system. The separated signals match those obtained using off-line Matlab-based analysis.

原文	English
主出版物標題	2012 IEEE Biomedical Circuits and Systems Conference
主出版物子標題	Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications
頁面	192-195
頁數	4
DOIs	https://doi.org/10.1109/BioCAS.2012.6418464
出版狀態	Published - 1 12月 2012
事件	2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Hsinchu, 台灣持續時間: 28 11月 2012 → 30 11月 2012

出版系列

名字	2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications

Conference

Conference	2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012
國家/地區	台灣
城市	Hsinchu
期間	28/11/12 → 30/11/12

存取文件

10.1109/BioCAS.2012.6418464

其它文件與鏈接

Link to publication in Scopus

引用此

Shih, W. Y., Huang, K. J., Chen, C. K., Fang, W.-C., Cauwenberghs, G., & Jung, T. P. (2012). An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm. 於 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications (頁 192-195). 文章 6418464 (2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications). https://doi.org/10.1109/BioCAS.2012.6418464

Shih, Wei Yeh ; Huang, Kuan Ju ; Chen, Chiu Kuo 等. / An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm. 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications. 2012. 頁 192-195 (2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications).

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title = "An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm",

abstract = "This paper presents an effective chip implementation of a real-time eight-channel electroencephalogram signal processor based on on-line recursive independent component analysis (ORICA) algorithm. The system architecture is composed of a memory unit, a whitening unit, an ORICA training unit, and an ORICA computation unit. The proposed architecture is implemented using TSMC 90 nm CMOS technology. It occupies a core area of 800×800 μm2 and consumes 4.18 mW at a core supply voltage of 1.0 V and 50 MHz clock operating frequency. Simulated super and sub-Gaussian signals are used to verify the system. The separated signals match those obtained using off-line Matlab-based analysis.",

author = "Shih, {Wei Yeh} and Huang, {Kuan Ju} and Chen, {Chiu Kuo} and Wai-Chi Fang and Gert Cauwenberghs and Jung, {Tzyy Ping}",

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Shih, WY, Huang, KJ, Chen, CK, Fang, W-C, Cauwenberghs, G & Jung, TP 2012, An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm. 於 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications., 6418464, 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications, 頁 192-195, 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012, Hsinchu, 台灣, 28/11/12. https://doi.org/10.1109/BioCAS.2012.6418464

An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm. / Shih, Wei Yeh; Huang, Kuan Ju; Chen, Chiu Kuo 等.
2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications. 2012. p. 192-195 6418464 (2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications).

研究成果: Conference contribution › 同行評審

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AU - Shih, Wei Yeh

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AU - Cauwenberghs, Gert

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AB - This paper presents an effective chip implementation of a real-time eight-channel electroencephalogram signal processor based on on-line recursive independent component analysis (ORICA) algorithm. The system architecture is composed of a memory unit, a whitening unit, an ORICA training unit, and an ORICA computation unit. The proposed architecture is implemented using TSMC 90 nm CMOS technology. It occupies a core area of 800×800 μm2 and consumes 4.18 mW at a core supply voltage of 1.0 V and 50 MHz clock operating frequency. Simulated super and sub-Gaussian signals are used to verify the system. The separated signals match those obtained using off-line Matlab-based analysis.

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Shih WY, Huang KJ, Chen CK, Fang WC, Cauwenberghs G, Jung TP. An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm. 於 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications. 2012. p. 192-195. 6418464. (2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications). doi: 10.1109/BioCAS.2012.6418464

An effective chip implementation of a real-time eight-channel EEG signal processor based on on-line recursive ICA algorithm

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Conference

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