An area-efficient relaxed half-stochastic decoding architecture for nonbinary LDPC codes

Keyphrases

• Decoder 100%
• Area-efficient 100%
• Stochastic Decoding 100%
• Non-binary LDPC Codes 100%
• Hardware Efficiency 40%
• Variable Node 40%
• Non-Binary Low-Density Parity-Check (NB-LDPC) 40%
• Decoding Algorithm 20%
• Hardware Complexity 20%
• Probability Density Function 20%
• Rate 1 20%
• Bit Error Rate Performance 20%
• Algorithm Complexity 20%
• Generation Method 20%
• Random number Generation 20%
• Sum-product Algorithm 20%
• Error Correction Capability 20%
• Track Prediction 20%
• Related Rates 20%
• Nonbinary Low-density Parity-check Codes 20%

Engineering

• Nodes 100%
• Hardware Complexity 50%
• Decoding Algorithm 50%
• Bit Error Rate 50%
• Random Number 50%
• Product Algorithm 50%
• Parity Check Code 50%
• Error Correcting Capability 50%
• Probability Density Function 50%

Computer Science

• Computer Hardware 100%
• Decoding Algorithm 33%
• Algorithmic Efficiency 33%
• Product Algorithm 33%
• Random Number Generation 33%
• low-density parity-check code 33%
• Probability Density Function 33%