An area-efficient high-throughput SM4 accelerator with SCA-countermeasure for TV applications

Wei Chiang*, Hsie Chia Chang, Chen-Yi Lee

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

The SM4 algorithm is the first commercial cipher published by China in 2012 which is widely used in WLAN WAPI resource restricted devices. This paper proposed the single-round-iterative architecture which can operate at 500 MHZ clock frequency and reach 2Gbps throughput. In order to resist side channel attack, we changed the S-box structure and add secret sharing during the computation process. According to the CPA result, this hardware is secure under the condition of collecting 1 million power traces. The gate count of this design is about 15.19k, gaining almost 17.7% area reduction to the BMTSM4 which can reach the similar throughput [1].

原文English
主出版物標題2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728133201
DOIs
出版狀態Published - 10月 2020
事件52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
持續時間: 10 10月 202021 10月 2020

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2020-October
ISSN(列印)0271-4310

Conference

Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
城市Virtual, Online
期間10/10/2021/10/20

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