An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory

J. P. Wu, M. Y. Lee, T. C. Kao, Y. J. Li, C. H. Liu, J. C. Guo, Steve S. Chung

研究成果: Conference contribution同行評審

摘要

In this paper, an ALL resistive neuromorphic computing (ARNC) platform was demonstrated with Restive-gate FinFET memory, which includes three major building blocks: weight, ReLU, and ADC. The weight consists of 4-bit-per-cell RG-FinFET memory arrays with gradual and symmetrical tuning capability of the conductance, reliable endurance up to 105 cycles for whole 16 states, and excellent data retention. ReLU shows linear output responses when the input is positive and sharply cut-off for negative input. The ADC was implemented by a 16 parallel RG-FinFETs, featuring 267 MHz of the operation frequency, 0.28μ W of the power at Vcc = 0.8V, and very small area size of 10-5 mm2. It is well-suited for the energy-efficient AI-Inference in CIM.

原文English
主出版物標題2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350334166
DOIs
出版狀態Published - 2023
事件2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan
持續時間: 17 4月 202320 4月 2023

出版系列

名字2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
國家/地區Taiwan
城市Hsinchu
期間17/04/2320/04/23

指紋

深入研究「An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory」主題。共同形成了獨特的指紋。

引用此