An analytical model for the power bipolar-MOS transistor

Di Son Kuo; Chen-Ming Hu; Steven P. Sapp

doi:10.1016/0038-1101(86)90128-0

An analytical model for the power bipolar-MOS transistor

Di Son Kuo^*, Chen-Ming Hu, Steven P. Sapp

^*此作品的通信作者

國際半導體產業學院

研究成果: Article › 同行評審

32 引文斯高帕斯（Scopus）

摘要

This paper presents an analytical model for the I-V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4-10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.

原文	English
頁（從 - 到）	1229-1237
頁數	9
期刊	Solid State Electronics
卷	29
發行號	12
DOIs	https://doi.org/10.1016/0038-1101(86)90128-0
出版狀態	Published - 1 1月 1986

存取文件

10.1016/0038-1101(86)90128-0

其它文件與鏈接

Link to publication in Scopus

引用此

@article{7a57a9b3fcd04cb68aed69b1e767b865,

title = "An analytical model for the power bipolar-MOS transistor",

abstract = "This paper presents an analytical model for the I-V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4-10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in VF. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase VF but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.",

author = "Kuo, {Di Son} and Chen-Ming Hu and Sapp, {Steven P.}",

year = "1986",

month = jan,

day = "1",

doi = "10.1016/0038-1101(86)90128-0",

language = "English",

volume = "29",

pages = "1229--1237",

journal = "Solid State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

number = "12",

}

TY - JOUR

T1 - An analytical model for the power bipolar-MOS transistor

AU - Kuo, Di Son

AU - Hu, Chen-Ming

AU - Sapp, Steven P.

PY - 1986/1/1

Y1 - 1986/1/1

N2 - This paper presents an analytical model for the I-V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4-10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in VF. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase VF but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.

AB - This paper presents an analytical model for the I-V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4-10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in VF. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase VF but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.

UR - http://www.scopus.com/inward/record.url?scp=0022873956&partnerID=8YFLogxK

U2 - 10.1016/0038-1101(86)90128-0

DO - 10.1016/0038-1101(86)90128-0

M3 - Article

AN - SCOPUS:0022873956

SN - 0038-1101

VL - 29

SP - 1229

EP - 1237

JO - Solid State Electronics

JF - Solid State Electronics

IS - 12

ER -

An analytical model for the power bipolar-MOS transistor

摘要

存取文件

其它文件與鏈接

指紋

引用此