An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Yi Wei Lin; Ming Chien Tsai; Hao I. Yang; Geng Cing Lin; Shao Cheng Wang; Ching Te Chuang; Shyh-Jye Jou; Wei Hwang; Nan Chun Lien; Kuen Di Lee; Wei Chiang Shih

doi:10.1109/VLSI-DAT.2012.6212589

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Yi Wei Lin^*, Ming Chien Tsai, Hao I. Yang, Geng Cing Lin, Shao Cheng Wang, Ching Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan Chun Lien, Kuen Di Lee, Wei Chiang Shih

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference contribution › 同行評審

摘要

We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V _read ) and cell Inverter Trip voltage (V _trip ) in SRAM cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of V _read and V _trip measurement scheme, and post-layout simulations show the resolution of the digital read-out scheme is 0.167mV/bit.

原文	English
主出版物標題	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-DAT.2012.6212589
出版狀態	Published - 25 7月 2012
事件	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, 台灣持續時間: 23 4月 2012 → 25 4月 2012

出版系列

名字	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
國家/地區	台灣
城市	Hsinchu
期間	23/04/12 → 25/04/12

存取文件

10.1109/VLSI-DAT.2012.6212589

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Link to publication in Scopus

引用此

Lin, Y. W., Tsai, M. C., Yang, H. I., Lin, G. C., Wang, S. C., Chuang, C. T., Jou, S.-J., Hwang, W., Lien, N. C., Lee, K. D., & Shih, W. C. (2012). An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers 文章 6212589 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212589

Lin, Yi Wei ; Tsai, Ming Chien ; Yang, Hao I. 等. / An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

@inproceedings{8f016df601c04f2f838e2f4a994d238d,

title = "An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array",

abstract = " We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V read ) and cell Inverter Trip voltage (V trip ) in SRAM cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of V read and V trip measurement scheme, and post-layout simulations show the resolution of the digital read-out scheme is 0.167mV/bit.",

author = "Lin, {Yi Wei} and Tsai, {Ming Chien} and Yang, {Hao I.} and Lin, {Geng Cing} and Wang, {Shao Cheng} and Chuang, {Ching Te} and Shyh-Jye Jou and Wei Hwang and Lien, {Nan Chun} and Lee, {Kuen Di} and Shih, {Wei Chiang}",

year = "2012",

month = jul,

day = "25",

doi = "10.1109/VLSI-DAT.2012.6212589",

language = "English",

isbn = "9781457720819",

series = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

booktitle = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

note = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 ; Conference date: 23-04-2012 Through 25-04-2012",

}

Lin, YW, Tsai, MC, Yang, HI, Lin, GC, Wang, SC, Chuang, CT, Jou, S-J, Hwang, W, Lien, NC, Lee, KD & Shih, WC 2012, An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212589, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, 台灣, 23/04/12. https://doi.org/10.1109/VLSI-DAT.2012.6212589

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. / Lin, Yi Wei; Tsai, Ming Chien; Yang, Hao I. 等.
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212589 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

AU - Lin, Yi Wei

AU - Tsai, Ming Chien

AU - Yang, Hao I.

AU - Lin, Geng Cing

AU - Wang, Shao Cheng

AU - Chuang, Ching Te

AU - Jou, Shyh-Jye

AU - Hwang, Wei

AU - Lien, Nan Chun

AU - Lee, Kuen Di

AU - Shih, Wei Chiang

PY - 2012/7/25

Y1 - 2012/7/25

N2 - We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V read ) and cell Inverter Trip voltage (V trip ) in SRAM cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of V read and V trip measurement scheme, and post-layout simulations show the resolution of the digital read-out scheme is 0.167mV/bit.

AB - We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V read ) and cell Inverter Trip voltage (V trip ) in SRAM cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of V read and V trip measurement scheme, and post-layout simulations show the resolution of the digital read-out scheme is 0.167mV/bit.

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U2 - 10.1109/VLSI-DAT.2012.6212589

DO - 10.1109/VLSI-DAT.2012.6212589

M3 - Conference contribution

AN - SCOPUS:84864075339

SN - 9781457720819

T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

T2 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012

Y2 - 23 April 2012 through 25 April 2012

ER -

Lin YW, Tsai MC, Yang HI, Lin GC, Wang SC, Chuang CT 等. An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212589. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212589

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

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