An all-digital phase-locked loop with a multi-delay-switching TDC

Chung Cheng Su, Cheng-Chung Lin, Chung-Chih Hung

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a low-power time-to-digital converter (TDC) with multi-delay-switching mechanism for ADPLL application. In order to achieve low power dissipation and low area occupation, a switching mechanism is proposed on TDC design. The proposed ADPLL achieves the frequency range from 150 MHz to 1.45 GHz and 18.4 ps peak-to-peak jitter at 800 MHz. The design has been implemented in 0.18 um CMOS process with an active area of 0.1088 mm2 and the whole system consumes 8.41 mW at 800 MHz.

原文English
主出版物標題2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509039692
DOIs
出版狀態Published - 5 6月 2017
事件2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan
持續時間: 24 4月 201727 4月 2017

出版系列

名字2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Conference

Conference2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
國家/地區Taiwan
城市Hsinchu
期間24/04/1727/04/17

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