An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Geng Cing Lin*, Shao Cheng Wang, Yi Wei Lin, Ming Chien Tsai, Ching Te Chuang, Shyh-Jye Jou, Nan Chun Lien, Wei Chiang Shih, Kuen Di Lee, Jyun Kai Chu

*此作品的通信作者

    研究成果: Paper同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to 45°C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.

    原文English
    頁面2485-2488
    頁數4
    DOIs
    出版狀態Published - 28 9月 2012
    事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
    持續時間: 20 5月 201223 5月 2012

    Conference

    Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
    國家/地區Korea, Republic of
    城市Seoul
    期間20/05/1223/05/12

    指紋

    深入研究「An all-digital bit transistor characterization scheme for CMOS 6T SRAM array」主題。共同形成了獨特的指紋。

    引用此