We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to 45°C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.
|出版狀態||Published - 28 9月 2012|
|事件||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of|
持續時間: 20 5月 2012 → 23 5月 2012
|Conference||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012|
|國家/地區||Korea, Republic of|
|期間||20/05/12 → 23/05/12|