TY - GEN
T1 - An 8 Gbps fast-locked automatic gain control for PAM receiver
AU - Wu, Guo Wei
AU - Chen, Wei-Zen
AU - Huang, Shih Hao
PY - 2009
Y1 - 2009
N2 - An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0,18 m CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 m W from a 1.8 V supply.
AB - An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0,18 m CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 m W from a 1.8 V supply.
KW - Automatic gain control (AGC)
KW - PAM receiver
KW - Variable gain amplifier
UR - http://www.scopus.com/inward/record.url?scp=76249133716&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2009.5357153
DO - 10.1109/ASSCC.2009.5357153
M3 - Conference contribution
AN - SCOPUS:76249133716
SN - 9781424444342
T3 - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
SP - 173
EP - 176
BT - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
T2 - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Y2 - 16 November 2009 through 18 November 2009
ER -