An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications

Chi Liu; Shao Tzu Li; Tong Lin Pan; Cheng En Ni; Yun Sung; Chia Lin Hu; Kang Yu Chang; Tuo Hung Hou; Tian Sheuan Chang; Shyh Jye Jou

doi:10.1109/VLSI-DAT54769.2022.9768058

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications

Chi Liu
, Shao Tzu Li
, Tong Lin Pan
, Cheng En Ni
, Yun Sung
, Chia Lin Hu
, Kang Yu Chang
, Tuo Hung Hou
, Tian Sheuan Chang
, Shyh Jye Jou^*

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A methodology for Artificial Intelligence (AI) edge Deep Convolutional Neural Network (DCNN) hardware design to increase computation parallelism and decrease latency is needed for a real time application. To increase the computation parallelism, a 1-bit by 1-bit high parallelism in-RRAM computing (IRC) macro is proposed. The goal of this testing macro is to test the characteristic of the RRAM and propose a co-training mechanism between DCNN algorithm and RRAM module to deal with the non-linearity issues of IRC.

原文	English
主出版物標題	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781665409216
DOIs	https://doi.org/10.1109/VLSI-DAT54769.2022.9768058
出版狀態	Published - 2022
事件	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, 台灣持續時間: 18 4月 2022 → 21 4月 2022

出版系列

名字	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
國家/地區	台灣
城市	Hsinchu
期間	18/04/22 → 21/04/22

存取文件

10.1109/VLSI-DAT54769.2022.9768058

其它文件與鏈接

Link to publication in Scopus

引用此

Liu, C., Li, S. T., Pan, T. L., Ni, C. E., Sung, Y., Hu, C. L., Chang, K. Y., Hou, T. H., Chang, T. S., & Jou, S. J. (2022). An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. 於 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT54769.2022.9768058

Liu, Chi ; Li, Shao Tzu ; Pan, Tong Lin 等. / An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).

@inproceedings{242cc22b39d849adbd33b387acbf42ea,

title = "An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications",

abstract = "A methodology for Artificial Intelligence (AI) edge Deep Convolutional Neural Network (DCNN) hardware design to increase computation parallelism and decrease latency is needed for a real time application. To increase the computation parallelism, a 1-bit by 1-bit high parallelism in-RRAM computing (IRC) macro is proposed. The goal of this testing macro is to test the characteristic of the RRAM and propose a co-training mechanism between DCNN algorithm and RRAM module to deal with the non-linearity issues of IRC.",

keywords = "CIFAR-10, Co-Training, Computing In-Memory, In-RRAM Computing",

author = "Chi Liu and Li, \{Shao Tzu\} and Pan, \{Tong Lin\} and Ni, \{Cheng En\} and Yun Sung and Hu, \{Chia Lin\} and Chang, \{Kang Yu\} and Hou, \{Tuo Hung\} and Chang, \{Tian Sheuan\} and Jou, \{Shyh Jye\}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 ; Conference date: 18-04-2022 Through 21-04-2022",

year = "2022",

doi = "10.1109/VLSI-DAT54769.2022.9768058",

language = "English",

series = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",

address = "美國",

}

Liu, C, Li, ST, Pan, TL, Ni, CE, Sung, Y, Hu, CL, Chang, KY, Hou, TH , Chang, TS & Jou, SJ 2022, An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. 於 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022, Hsinchu, 台灣, 18/04/22. https://doi.org/10.1109/VLSI-DAT54769.2022.9768058

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. / Liu, Chi; Li, Shao Tzu; Pan, Tong Lin 等.
2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications

AU - Liu, Chi

AU - Li, Shao Tzu

AU - Pan, Tong Lin

AU - Ni, Cheng En

AU - Sung, Yun

AU - Hu, Chia Lin

AU - Chang, Kang Yu

AU - Hou, Tuo Hung

AU - Chang, Tian Sheuan

AU - Jou, Shyh Jye

PY - 2022

Y1 - 2022

N2 - A methodology for Artificial Intelligence (AI) edge Deep Convolutional Neural Network (DCNN) hardware design to increase computation parallelism and decrease latency is needed for a real time application. To increase the computation parallelism, a 1-bit by 1-bit high parallelism in-RRAM computing (IRC) macro is proposed. The goal of this testing macro is to test the characteristic of the RRAM and propose a co-training mechanism between DCNN algorithm and RRAM module to deal with the non-linearity issues of IRC.

AB - A methodology for Artificial Intelligence (AI) edge Deep Convolutional Neural Network (DCNN) hardware design to increase computation parallelism and decrease latency is needed for a real time application. To increase the computation parallelism, a 1-bit by 1-bit high parallelism in-RRAM computing (IRC) macro is proposed. The goal of this testing macro is to test the characteristic of the RRAM and propose a co-training mechanism between DCNN algorithm and RRAM module to deal with the non-linearity issues of IRC.

KW - CIFAR-10

KW - Co-Training

KW - Computing In-Memory

KW - In-RRAM Computing

UR - https://www.scopus.com/pages/publications/85130463943

U2 - 10.1109/VLSI-DAT54769.2022.9768058

DO - 10.1109/VLSI-DAT54769.2022.9768058

M3 - Conference contribution

AN - SCOPUS:85130463943

T3 - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

BT - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022

Y2 - 18 April 2022 through 21 April 2022

ER -

Liu C, Li ST, Pan TL, Ni CE, Sung Y, Hu CL 等. An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. 於 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings). doi: 10.1109/VLSI-DAT54769.2022.9768058

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications

摘要

出版系列

Conference

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