An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications

Chi Liu, Shao Tzu Li, Tong Lin Pan, Cheng En Ni, Yun Sung, Chia Lin Hu, Kang Yu Chang, Tuo Hung Hou, Tian Sheuan Chang, Shyh Jye Jou*

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

A methodology for Artificial Intelligence (AI) edge Deep Convolutional Neural Network (DCNN) hardware design to increase computation parallelism and decrease latency is needed for a real time application. To increase the computation parallelism, a 1-bit by 1-bit high parallelism in-RRAM computing (IRC) macro is proposed. The goal of this testing macro is to test the characteristic of the RRAM and propose a co-training mechanism between DCNN algorithm and RRAM module to deal with the non-linearity issues of IRC.

原文English
主出版物標題2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665409216
DOIs
出版狀態Published - 2022
事件2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, Taiwan
持續時間: 18 4月 202221 4月 2022

出版系列

名字2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
國家/地區Taiwan
城市Hsinchu
期間18/04/2221/04/22

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