ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping

Juinn-Dar Huang, Jing Yang Jou, Wen Zen Shen

研究成果: Article同行評審

19 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based field programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimized one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.

原文English
頁(從 - 到)392-400
頁數9
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
8
發行號4
DOIs
出版狀態Published - 8月 2000

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