Alternate hammering test for application-specific DRAMs and an industrial case study

Rei Fu Huang*, Hao Yu Yang, Chia-Tso Chao, Shih Chin Lin

*此作品的通信作者

    研究成果: Conference contribution同行評審

    15 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.

    原文English
    主出版物標題Proceedings of the 49th Annual Design Automation Conference, DAC '12
    頁面1012-1017
    頁數6
    DOIs
    出版狀態Published - 11 7月 2012
    事件49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
    持續時間: 3 6月 20127 6月 2012

    出版系列

    名字Proceedings - Design Automation Conference
    ISSN(列印)0738-100X

    Conference

    Conference49th Annual Design Automation Conference, DAC '12
    國家/地區United States
    城市San Francisco, CA
    期間3/06/127/06/12

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