In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm2.
|出版狀態||Published - 1 12月 1998|
|事件||Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal|
持續時間: 7 9月 1998 → 10 9月 1998
|Conference||Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology|
|期間||7/09/98 → 10/09/98|