All-digital fast-locking pulsewidth-control circuit with programmable duty cycle

This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This paper presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the two-stage matrix converter 0.18-μrm m CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600 MHz, and an input duty cycle ranging from 30% to 70%. It achieves a programmable output duty cycle ranging from 31.25% to 68.75% in increments of 6.25%.