All digital 625Mbps & 2.5Gbps deskew buffer design

Hung W. Lu*, Yin T. Chang, Chau-Chin Su

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper describes an all digital 625Mbps and 2.5Gbps de-skew design for data recovery. It uses a confidence counter to serve as the loop filler that greatly reduces the circuit complexity and improves the jitter compression. The 625Mbps version has been implemented using TSMC 0.18um 1P6M CMOS technology. Measurement results show that the phase resolution is 100ps and the de-skew range is 1.6ns. The output jitter is 48ps and the power consumption is 3.8 mW. For the 2.5Gbps version, the simulation results show that the timing resolution is 26ps, the total de-skew range is 400ps, the output jitter is 26.5ps, and the power consumption is 16 mW.

原文English
主出版物標題2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
頁面263-266
頁數4
DOIs
出版狀態Published - 27 四月 2005
事件2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
持續時間: 27 四月 200529 四月 2005

出版系列

名字2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
國家/地區Taiwan
城市Hsinchu
期間27/04/0529/04/05

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