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Aging-aware timing analysis and optimization considering path sensitization
Kai-Chiang Wu
*
, Diana Marculescu
*
此作品的通信作者
資訊科學與工程研究所
研究成果
:
Conference contribution
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同行評審
19
引文 斯高帕斯(Scopus)
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Keyphrases
Timing Analysis
100%
Timing Optimization
100%
Path Sensitization
100%
Aging-aware
100%
Aging
50%
Circuit Delay
50%
Supply Voltage
25%
Thin Gate Oxide
25%
Downscaling
25%
Circuit Performance
25%
Performance Loss
25%
Technology Scaling
25%
Performance Degradation
25%
Area Overhead
25%
Circuit Lifetime
25%
Significant Loss
25%
Subcircuit
25%
Efficient Optimization
25%
Reliability Degradation
25%
Scaling Trends
25%
Device Aging
25%
Early Design Phases
25%
Nanoscale Design
25%
Optimization Flow
25%
Engineering
Delay Circuits
100%
Supply Voltage
50%
Nanoscale
50%
Gate Oxide
50%
Critical Path
50%
Circuit Performance
50%
Performance Loss
50%
Main Factor
50%
Area Overhead
50%
Design Stage
50%
Subcircuit
50%
Performance Degradation
50%
Computer Science
Timing Analysis
100%
Timing Optimization
100%
Supply Voltage
50%
Critical Path
50%
Performance Loss
50%
Performance Degradation
50%
Early Design Stage
50%