Aging-aware chip health prediction adopting an innovative monitoring strategy

Yun Ting Wang, Kai-Chiang Wu, Chung Han Chou, Shih Chieh Chang

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

Concerns exist that the reliability of chips is worsening because of downscaling technology. Among various reliability challenges, device aging is a dominant concern because it degrades circuit performance over time. Traditionally, runtime monitoring approaches are proposed to estimate aging effects. However, such techniques tend to predict and monitor delay degradation status for circuit mitigation measures rather than the health condition of the chip. In this paper, we propose an aging-aware chip health prediction methodology that adapts to workload conditions and process, supply voltage, and temperature variations. Our prediction methodology adopts an innovative on-chip delay monitoring strategy by tracing representative aging-aware delay behavior. The delay behavior is then fed into a machine learning engine to predict the age of the tested chips. Experimental results indicate that our strategy can obtain 97.40% accuracy with 4.14% area overhead on average. To the authors' knowledge, this is the first method that accurately predicts current chip age and provides information regarding future chip health.

原文English
主出版物標題ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面179-184
頁數6
ISBN(電子)9781450360074
DOIs
出版狀態Published - 21 1月 2019
事件24th Asia and South Pacific Design Automation Conference, ASPDAC 2019 - Tokyo, Japan
持續時間: 21 1月 201924 1月 2019

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference24th Asia and South Pacific Design Automation Conference, ASPDAC 2019
國家/地區Japan
城市Tokyo
期間21/01/1924/01/19

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