AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks

Kris Tiri*, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede

*此作品的通信作者

研究成果: Conference contribution同行評審

25 引文 斯高帕斯(Scopus)

摘要

This paper describes an embedded security coprocessor that consists of four components: an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-μm process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses Wave Dynamic Differential Logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.

原文English
主出版物標題2005 Symposium on VLSI Circuits - Digest of Technical Papers
頁面216-219
頁數4
DOIs
出版狀態Published - 1 12月 2005
事件2005 Symposium on VLSI Circuits - Kyoto, Japan
持續時間: 16 6月 200518 6月 2005

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2005

Conference

Conference2005 Symposium on VLSI Circuits
國家/地區Japan
城市Kyoto
期間16/06/0518/06/05

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