Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability

Ming-Dou Ker*, Chung-Yu Wu, Tung Yang Chen

*此作品的通信作者

研究成果: Paper同行評審

摘要

Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

原文English
頁面45-49
頁數5
DOIs
出版狀態Published - 1 1月 1997
事件Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
持續時間: 3 6月 19975 6月 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
城市Taipei, China
期間3/06/975/06/97

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