Adaptive quadrature clock generator

Juin Hau Huang; Chih Hsien Lin; Shyh-Jye Jou

doi:10.1109/VDAT.2006.258160

Adaptive quadrature clock generator

Juin Hau Huang^*, Chih Hsien Lin, Shyh-Jye Jou

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13μm 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz.

原文	English
主出版物標題	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
頁面	203-206
頁數	4
DOIs	https://doi.org/10.1109/VDAT.2006.258160
出版狀態	Published - 2007
事件	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, 台灣持續時間: 26 4月 2007 → 28 4月 2007

出版系列

名字	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
國家/地區	台灣
城市	Hsinchu
期間	26/04/07 → 28/04/07

存取文件

10.1109/VDAT.2006.258160

其它文件與鏈接

Link to publication in Scopus

引用此

Huang, J. H., Lin, C. H., & Jou, S.-J. (2007). Adaptive quadrature clock generator. 於 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (頁 203-206). 文章 4027532 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258160

@inproceedings{631db1ea521444a585b99639a5b84fa7,

title = "Adaptive quadrature clock generator",

abstract = "In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13μm 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz.",

author = "Huang, {Juin Hau} and Lin, {Chih Hsien} and Shyh-Jye Jou",

year = "2007",

doi = "10.1109/VDAT.2006.258160",

language = "English",

isbn = "1424401798",

series = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

pages = "203--206",

booktitle = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

note = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 ; Conference date: 26-04-2007 Through 28-04-2007",

}

Huang, JH, Lin, CH & Jou, S-J 2007, Adaptive quadrature clock generator. 於 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027532, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, 頁 203-206, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, 台灣, 26/04/07. https://doi.org/10.1109/VDAT.2006.258160

Adaptive quadrature clock generator. / Huang, Juin Hau; Lin, Chih Hsien; Jou, Shyh-Jye.
2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 203-206 4027532 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Adaptive quadrature clock generator

AU - Huang, Juin Hau

AU - Lin, Chih Hsien

AU - Jou, Shyh-Jye

PY - 2007

Y1 - 2007

N2 - In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13μm 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz.

AB - In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13μm 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz.

UR - http://www.scopus.com/inward/record.url?scp=34748873197&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2006.258160

DO - 10.1109/VDAT.2006.258160

M3 - Conference contribution

AN - SCOPUS:34748873197

SN - 1424401798

SN - 9781424401796

T3 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

SP - 203

EP - 206

BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

T2 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006

Y2 - 26 April 2007 through 28 April 2007

ER -

Adaptive quadrature clock generator

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