Active ESD protection for input transistors in a 40-nm CMOS process

Federico A. Altolaguirre; Ming-Dou Ker

doi:10.1109/VLSI-DAT.2015.7114533

Active ESD protection for input transistors in a 40-nm CMOS process

Federico A. Altolaguirre, Ming-Dou Ker

照明與能源光電研究所

研究成果: Conference contribution › 同行評審

4 引文斯高帕斯（Scopus）

摘要

This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

原文	English
主出版物標題	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114533
出版狀態	Published - 28 5月 2015
事件	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan 持續時間: 27 4月 2015 → 29 4月 2015

出版系列

名字	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
國家/地區	Taiwan
城市	Hsinchu
期間	27/04/15 → 29/04/15

存取文件

10.1109/VLSI-DAT.2015.7114533

其它文件與鏈接

Link to publication in Scopus

引用此

Altolaguirre, F. A., & Ker, M-D. (2015). Active ESD protection for input transistors in a 40-nm CMOS process. 於 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 [7114533] (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114533

@inproceedings{7c8da89b16db4f188d046056a850d254,

title = "Active ESD protection for input transistors in a 40-nm CMOS process",

abstract = "This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.",

keywords = "CMOS ICs, ESD, ESD protection, Reliability",

author = "Altolaguirre, {Federico A.} and Ming-Dou Ker",

year = "2015",

month = may,

day = "28",

doi = "10.1109/VLSI-DAT.2015.7114533",

language = "English",

series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

address = "United States",

note = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

}

Altolaguirre, FA & Ker, M-D 2015, Active ESD protection for input transistors in a 40-nm CMOS process. 於 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114533, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 27/04/15. https://doi.org/10.1109/VLSI-DAT.2015.7114533

Active ESD protection for input transistors in a 40-nm CMOS process. / Altolaguirre, Federico A.; Ker, Ming-Dou.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114533 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Active ESD protection for input transistors in a 40-nm CMOS process

AU - Altolaguirre, Federico A.

AU - Ker, Ming-Dou

PY - 2015/5/28

Y1 - 2015/5/28

N2 - This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

AB - This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

KW - CMOS ICs

KW - ESD

KW - ESD protection

KW - Reliability

UR - http://www.scopus.com/inward/record.url?scp=84936972745&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2015.7114533

DO - 10.1109/VLSI-DAT.2015.7114533

M3 - Conference contribution

AN - SCOPUS:84936972745

T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Y2 - 27 April 2015 through 29 April 2015

ER -

Active ESD protection for input transistors in a 40-nm CMOS process

摘要

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Conference

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