@inproceedings{f7f9a86870db495b8d96e9b678d42ff0,
title = "Active device under bond pad to save I/O layout for high-pin-count SOC",
abstract = "To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35 μm one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).",
keywords = "Bonding, CMOS process, Electrostatic discharge, Leakage current, MOS devices, Protection, Stress, System-on-a-chip, Testing, Threshold voltage",
author = "Ming-Dou Ker and Peng, {Jeng Jie} and Jiang, {Hsin Chin}",
note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 4th International Symposium on Quality Electronic Design, ISQED 2003 ; Conference date: 24-03-2003 Through 26-03-2003",
year = "2003",
doi = "10.1109/ISQED.2003.1194738",
language = "English",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "241--246",
booktitle = "Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003",
address = "美國",
}