Achieving Analog Layout Integrity through Learning and Migration Invited Talk

Mark Po Hung Lin, Hao Yu Chi, Abhishek Patyal, Zheng Yao Liu, Jun Jie Zhao, Chien-Nan Liu, Hung-Ming Chen

研究成果: Conference article同行評審

2 引文 斯高帕斯(Scopus)

摘要

Analog IC designers and design houses have been accumulating their own design knowledge and constructing their own analog design repositories, including various design specifications, applications, and process technologies. As most of the analog layouts are handcrafted art works, different designers/companies may have different layout guidelines and preferences. When generating a new layout for certain analog design which already exists or is similar to any of those in the repositories, but with different circuit parameters or process technology files, applying layout migration is usually more preferable than starting from scratch. This paper introduces a holistic framework and new layout generation methodology to achieve analog layout integrity through learning and migration. The introduced methodology can effectively and efficiently preserve the preferences of placement and routing topologies from legacy layouts to new ones.

原文English
文章編號9256451
期刊IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
2020-November
DOIs
出版狀態Published - 2 11月 2020
事件39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020 - Virtual, San Diego, United States
持續時間: 2 11月 20205 11月 2020

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