A wide-range capacitance-to-frequency readout circuit using pulse-width detection and delay-line-based feedback control loop

This paper presents a capacitive sensor readout IC with low power consumption and an extensive linear range. The proposed capacitance readout circuitry adopts capacitor-to-frequency (C2F) architecture to suppress the effect of amplitude noise by converting the analog signal to frequency. Then, the inverter-based time-to-digital converter (DTDC) digitalizes the frequency information. A feedback loop with a switchable capacitive bank to lock the C2F input capacitance and adjustable conversion rate are employed to enhance the linear capacitance detection range. The pulse width in a period represents the detected capacitance information. The design was fabricated in a 0.18 μm CMOS process, and the chip area is 1.38 mm². The proposed design achieves linearities of 0.9999, 0.9999, and 0.9965, whereas the sensitivity is adjusted to 5.6, 14.9, and 2 μs/pF, respectively. The Allen deviation floor of C2F is 0.97 Hz, and the sensing capacitance range is 20-90 pF while only consuming 31 μW.