A wide-range burst mode clock and data recovery circuit

Wei-Zen Chen; Chin Yuan Wei; Jen Wen Chen

doi:10.1109/ASSCC.2006.357936

A wide-range burst mode clock and data recovery circuit

Wei-Zen Chen^*, Chin Yuan Wei, Jen Wen Chen

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研究成果: Paper › 同行評審

3 引文斯高帕斯（Scopus）

摘要

This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 ^-10.

原文	English
頁面	403-406
頁數	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357936
出版狀態	Published - 2006
事件	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China 持續時間: 13 11月 2006 → 15 11月 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
國家/地區	China
城市	Hangzhou
期間	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357936

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Link to publication in Scopus

引用此

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title = "A wide-range burst mode clock and data recovery circuit",

abstract = "This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.",

author = "Wei-Zen Chen and Wei, {Chin Yuan} and Chen, {Jen Wen}",

year = "2006",

doi = "10.1109/ASSCC.2006.357936",

language = "English",

pages = "403--406",

note = "2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 ; Conference date: 13-11-2006 Through 15-11-2006",

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AU - Wei, Chin Yuan

AU - Chen, Jen Wen

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N2 - This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.

AB - This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.

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A wide-range burst mode clock and data recovery circuit

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