@inproceedings{c5f0800b533e49ca95ca477fc3777d77,
title = "A well-structured modified booth multiplier design",
abstract = "This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved Booth encoder and selector to achieve an extra-row-removal and a hybrid spare-tree approach to design two's complementation circuit to both reduce the area and improve the speed. Experimental results on a 32 bit multiplier show that it obtains area and power savings of 15.8% and 11.7% respectively over the classical design and of 7.5% and 5.5% respectively over the design of the best performance reported so far.",
author = "Wang, {Li Rong} and Shyh-Jye Jou and Lee, {Chung Len}",
year = "2008",
month = sep,
day = "5",
doi = "10.1109/VDAT.2008.4542418",
language = "English",
isbn = "9781424416172",
series = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",
pages = "85--88",
booktitle = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",
note = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT ; Conference date: 23-04-2008 Through 25-04-2008",
}