A well-structured modified booth multiplier design

Li Rong Wang*, Shyh-Jye Jou, Chung Len Lee

*此作品的通信作者

    研究成果: Conference contribution同行評審

    17 引文 斯高帕斯(Scopus)

    摘要

    This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved Booth encoder and selector to achieve an extra-row-removal and a hybrid spare-tree approach to design two's complementation circuit to both reduce the area and improve the speed. Experimental results on a 32 bit multiplier show that it obtains area and power savings of 15.8% and 11.7% respectively over the classical design and of 7.5% and 5.5% respectively over the design of the best performance reported so far.

    原文English
    主出版物標題2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
    頁面85-88
    頁數4
    DOIs
    出版狀態Published - 5 9月 2008
    事件2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan
    持續時間: 23 4月 200825 4月 2008

    出版系列

    名字2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

    Conference

    Conference2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
    國家/地區Taiwan
    城市Hsinchu
    期間23/04/0825/04/08

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