A VLSI design of singular value decomposition processor used in real-time ICA computation for multi-channel EEG system

Kuan Ju Huang, Wei Yeh Shih, Jui Chieh Liao, Wai-Chi  Fang

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper presents a VLSI design of singular value decomposition (SVD) processor used in real-time independent component analysis (ICA) computation for multi-channel electroencephalography (EEG) system. EEG signals are easily influenced by other artifacts. To acquire artifact free EEG signals, ICA is a popular method for artifact removal. Results obtained after the pre-processing of ICA are often used for further applications such as brain computer interfaces (BCIs). In order to improve the feasibility and convenience of BCIs, a real-time ICA pre-processing is required. Because SVD is used frequently in computations of ICA, a SVD processor used for real-time ICA computation is essential. This paper aims to develop a custom SVD for multi-channel EEG systems based on ICA. During the ICA process, the proposed processor aims to solve the inverse and inverse square root matrices in real time. And the processor obtains a highly accurate result since a novel design concept for renewing data flow and parallel data processing are provided in this research. This processor is developed with TSMC 90nm CMOS technology in an 8-channel EEG system. The performance of the proposed SVD is also provided with the processing result of the EEG system.

原文English
主出版物標題2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
頁面413-416
頁數4
DOIs
出版狀態Published - 2013
事件2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, 中國
持續時間: 19 5月 201323 5月 2013

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
國家/地區中國
城市Beijing
期間19/05/1323/05/13

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