TY - JOUR
T1 - A universal VLSI architecture for Reed-Solomon error-and-erasure decoders
AU - Chang, Hsie-Chia
AU - Lin, Chein Ching
AU - Chang, Fu Ke
AU - Lee, Chen-Yi
PY - 2009/9/24
Y1 - 2009/9/24
N2 -
This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-μm 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm
2
silicon area, and the average core power consumption is 68.1 mW.
AB -
This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-μm 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm
2
silicon area, and the average core power consumption is 68.1 mW.
KW - Error-and-erasure correction
KW - Montgomery multiplication
KW - Reed-Solomon (RS) code
KW - Universal architecture
UR - http://www.scopus.com/inward/record.url?scp=70349257434&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2008.2010143
DO - 10.1109/TCSI.2008.2010143
M3 - Article
AN - SCOPUS:70349257434
SN - 1549-8328
VL - 56
SP - 1960
EP - 1967
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 9
ER -