A unified processor architecture for RISC & VLIW DSP

Keyphrases

• VLIW DSP 100%
• Processor Architecture 100%
• RISC 100%
• Operation Mode 66%
• Processor Core 66%
• 4-way 33%
• CMOS Technology 33%
• Core Size 33%
• Compiler 33%
• 0.18-μm CMOS Technology 33%
• On-chip Memory 33%
• Average Power 33%
• Code Size 33%
• Data Manipulation 33%
• Ping-pong 33%
• Stream Processing 33%
• Instruction Encoding 33%
• Program Flow 33%
• Control Construct 33%

Computer Science

• Processor Architectures 100%
• Processor Core 100%
• Operation Mode 100%
• Datapath 50%
• Data Manipulation 50%
• Stream Processing 50%
• Single Program 50%
• Computer Hardware 50%