A unified analog synthesis approach considering parasitic effects and process variations

Manually designing the analog/RF and power circuits to meet requirements is often considered a difficult task that takes a lot of time. Several automatic circuit-sizing approaches have been proposed for typical analog circuits to solve this bottleneck, but the performance and yield is unexpected if the non-ideal effects are not considered. In this chapter, an equation-based automatic synthesis approach for analog circuits is proposed. The layout-induced parasitic effects and process variations are also considered simultaneously to guarantee the circuit performance after manufacturing. As shown in the experimental results, the proposed approach successfully solves the unreachable specification in previous work and keeps the performance and yield of the generated circuit even in post-layout simulations. The incurred hardware overhead is also reduced by using the proposed unified approach, which demonstrates the feasibility and efficiency of this approach.