A Two-Stage Path Planning Engine for Robot Navigation System

Yu En Hsu, Yen Chin Liao, Hsie Chia Chang

研究成果: Conference contribution同行評審

摘要

This paper presents a two-stage path planning architecture, realized by using a general-purpose CPU as a global planner and a proposed path planning engine as a local planner, solving a path planning problem hierarchically. By the use of heterogeneity, the hardware-software cooperation architecture can take advantages of both hardware and software approach and achieve both generalization and hardware-acceleration. The proposed path planning engine is based on A∗ algorithm, several hardware-friendly optimization techniques are applied or proposed to reduce the time complexity of searching. The coefficient modification avoids the usage of square root hardware. Then, the priority list reordering fully utilizes the memory bandwidth. Finally, we optimized the critical path and achieved 333MHz operating frequency.The proposed system is established and verified in Xilinx PYNQ-Z2 platform using ARM A9 processor as global planner and FPGA as local planner. Moreover, the proposed path planning engine is implemented in TSMC 40nm CMOS process and integrated 296.1k logic gates in 0.28mm2 chip area. It achieves 9.6μs/task latency and 0.16μJ/task energy consumption in 2D and 27.6μs/task latency and 0.48μJ/task energy consumption in 3D.

原文English
主出版物標題Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021
編輯Gang Qu, Jinjun Xiong, Danella Zhao, Venki Muthukumar, Md Farhadur Reza, Ramalingam Sridhar
發行者IEEE Computer Society
頁面218-223
頁數6
ISBN(電子)9781665429313
DOIs
出版狀態Published - 2021
事件34th IEEE International System-on-Chip Conference, SOCC 2021 - Virtual, Online, 美國
持續時間: 14 9月 202117 9月 2021

出版系列

名字International System on Chip Conference
2021-September
ISSN(列印)2164-1676
ISSN(電子)2164-1706

Conference

Conference34th IEEE International System-on-Chip Conference, SOCC 2021
國家/地區美國
城市Virtual, Online
期間14/09/2117/09/21

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