@inproceedings{dcc60591fa1f494ebeac0a5d4b17ada2,
title = "A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW",
abstract = "This paper presents a two-step incremental ADC (lADC) using extended counting. In the first step, the lADC is configured as a first-order ΔΣ loop with an input feedforward architecture. In the second step, a two-capacitor SAR-assisted extended counting technique enhances the accuracy. A single active integrator is shared in both steps. Fabricated in 0.18-μm CMOS process, the IADC achieves a peak SNR/SNDR/DR of 97.1/96.6/100.2 dB over a 1.2 kHz bandwidth, while dissipating 33.2 μW from a 1.5 V supply. This gives a Schreier FoM of 175.8 dB and Walden FoM of 0.25 pJ/conv.-step, both among the best values.",
keywords = "delta-sigma, extended counting, multi-step incremental ADC, SAR-assisted, two-capacitor",
author = "Yi Zhang and Chia-Hung Chen and Tao He and Kazuki Sobue and Koichi Hamashita and Temes, {Gabor C.}",
year = "2017",
month = jul,
day = "26",
doi = "10.1109/CICC.2017.7993660",
language = "English",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "38th Annual Custom Integrated Circuits Conference",
address = "United States",
note = "38th Annual Custom Integrated Circuits Conference, CICC 2017 ; Conference date: 30-04-2017 Through 03-05-2017",
}