A threshold-embedded offset calibration technique for folding flash ADCs

A threshold-embedded offset calibration technique for inverter-based analog-to-digital converter (ADC) is presented. This work presents a background calibration technique for trimming the input-referred offsets of the comparators without interrupting the ADC's normal operation. Moreover, a folding flash architecture is employed to save the conversion power. The proposed calibration approach is based on the time-domain comparison. The random input-referred offsets of the comparators are converted to phase difference and detected by time-domain comparators. Simulation results show that the proposed compensation technique is validated. After calibration, the effective number of bits (ENOB) can be significantly improved from 3.4 bit to 5.7 bit.