A systematic approach to correlation analysis of in-line process parameters for process variation effect on electrical characteristic of 16-nm HKMG Bulk FinFET devices

Ping Hsun Su*, Yi-ming Li

*此作品的通信作者

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5 引文 斯高帕斯(Scopus)

摘要

This paper reports a systematic method to discover and optimize key fabrication in-line process of 16-nm high-κ metal gate bulk FinFET to improve device's performance and variability. The sensitivity analysis is utilized to prioritize key in-line process parameters which significantly boost device's performance and effectively reduce its variations. To extract hidden correlations among complex and a large number of in-line process parameters, data mining technique is applied to highlight and group-associated in-line process parameters. The source of variations of in-line process parameters in each group is revealed and the optimized solution is proposed to reduce its sensitivity to devices' fluctuation. Results show the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant are grouped to the same cluster and significantly affect the threshold voltage (Vt,sat), the on-state current (Id,sat), and the off-state current (Id,off), but the key variation source of these parameters is the thickness of the dual gate-spacer. By replacing dual spacers with single spacers, the fluctuation of threshold voltage is 30% dropped.

原文English
文章編號7500068
頁(從 - 到)209-216
頁數8
期刊IEEE Transactions on Semiconductor Manufacturing
29
發行號3
DOIs
出版狀態Published - 八月 2016

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