@inproceedings{c1bcacb239bb47eaa28443d1b59f3e15,
title = "A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper",
abstract = "We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.",
author = "Chiu, {Yi Wei} and Hu, {Yu Hao} and Zhao, {Jun Kai} and Shyh-Jye Jou and Chuang, {Ching Te}",
year = "2016",
month = jul,
day = "29",
doi = "10.1109/ISCAS.2016.7527415",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1014--1017",
booktitle = "ISCAS 2016 - IEEE International Symposium on Circuits and Systems",
address = "United States",
note = "2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 ; Conference date: 22-05-2016 Through 25-05-2016",
}