TY - GEN
T1 - A Structure-Based Methodology for Analog Layout Generation
AU - Chen, Yu Hsien
AU - Chi, Hao Yu
AU - Song, Ling Yen
AU - Liu, Chien Nan Jimmy
AU - Chen, Hung Ming
PY - 2019/7
Y1 - 2019/7
N2 - In order to speed up analog design cycles, analog layout automation is a popular research in recent years. However, most previous works assume that the required design constraints are given by users manually. Designers still take a lot of time to fill-in the required design information. Template-based layout generation is another approach to consider the design constraints, but considerable development efforts are required for each new design and each new technology. In this paper, we propose a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users' input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users' intervention and still keeps the post-layout performance within specifications.
AB - In order to speed up analog design cycles, analog layout automation is a popular research in recent years. However, most previous works assume that the required design constraints are given by users manually. Designers still take a lot of time to fill-in the required design information. Template-based layout generation is another approach to consider the design constraints, but considerable development efforts are required for each new design and each new technology. In this paper, we propose a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users' input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users' intervention and still keeps the post-layout performance within specifications.
UR - http://www.scopus.com/inward/record.url?scp=85071575010&partnerID=8YFLogxK
U2 - 10.1109/SMACD.2019.8795227
DO - 10.1109/SMACD.2019.8795227
M3 - Conference contribution
AN - SCOPUS:85071575010
T3 - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
SP - 33
EP - 36
BT - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
Y2 - 15 July 2019 through 18 July 2019
ER -